Principal Engineer, ASIC Development Engineering (Physical verification Engineer)

JOB Description :
 

• Take the leadership role of executing and signing off physical verification for block and full chip.
• Strong fundamentals in physical design verification using Calibre tool.
• Strong experience in multi voltage domain and design experience with multi-million instances.
• Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeouts
• Experience of working in lower tech nodes (TSMC5nm and below)
• Familiarity of PnR flows and tools such as Cadence Innovus/FC is must.
• Knowledge and hands on virtuoso experience is plus.
• Experience in power gating digital designs is a plus.
• Excellent verbal and written communication skills are required.
• Perform block and full-chip physical verification and work with the physical design team to close design issues
• Experience level : Minimum 8 to 12 years

Bachelor’s/Masters’ degree in Electronics and communication, Electronics and Electrical engineering

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.