Staff Engineer, ASIC Development Engineering ( System Verilog and UVM, Verilog)

Experience in ASIC verification, Expertise in System Verilog and UVM, Verilog.

·        Experience in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations.

·        The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently.

·        Knowledge on serial protocols UFS, PCIe, USB, MIPI or any other serial protocol. Knowledge on memory protocols - AXI, PCIE, UFS and Flash etc.

·        Knowledge on scripting languages like Python, Perl etc.

·        Keen on continuous process improvement to improve Quality and time

Bachelor of Engineering 

4-7 years of experience 

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