Sr. Staff ASIC Verification Engineer

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. Role Summary We are seeking a high-caliber Sr. Staff Verification Engineer to join our ADAS and Inference Silicon team. You will be responsible for the end-to-end functional verification of our next-generation SoC. Responsibilities Drive end-to-end functional and performance verification of AI accelerator architectures: Ensure bit-accurate numerical integrity and high-bandwidth dataflow for production-scale CNN and Transformer workloads. Verification Methodology: Leverage SystemVerilog/UVM for Coverage-Driven Verification (CDV) to reach aggressive functional targets. Apply Formal Verification (SVA) to exhaustively prove corner cases in safety-critical arbiters, state machines, and concurrency logic where simulation falls short. Advanced Methodologies (nice-to-have): Strategize and Implement LLM-augmented workflows for Front End Development. Safety-Critical Verification (nice-to-have): Develop and execute verification plans compliant with ISO 26262 standards. Conduct Fault Injection Analysis (FIA) to verify safety mechanisms (ECC, Parity, BIST). Hardware-Software Co-Verification (nice-to-have): Collaborate with firmware teams using Emulation and FPGA prototyping to run full-stack software. Qualifications Experience: Typically 10+ years of industry experience in ASIC design verification. Engineers who have seen multiple chips from "concept to tape-out." Education: BS/MS or PhD in Electrical Engineering or Computer Engineering. Hardware Knowledge: Deep understanding of Computer Architecture. Memory hierarchies (Cache, DMA, and DDR/HBM). Interconnect protocols (NoC - Network on Chip). Low-power design verification (UPF/CPF). Bonus Skills / Experience: Specialized hardware like Systolic Arrays, Vector Processors, or Neural Processing Units (NPUs). Understanding of how CNN and Transformer networks map to hardware. Compilers and toolchains Pay Disclosure The salary range for this role is $237,000 - $296,000 for Palo Alto based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for annual performance bonus and equity awards. We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com. You can apply for this role through careers.rivian.com (or through internal-careers-rivian.icims.com if you are a current employee). This job is not expected to be closed any sooner than April 30, 2026. Equal Opportunity Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law. Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com. Candidate Data Privacy Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. 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Drive end-to-end functional and performance verification of AI accelerator architectures: Ensure bit-accurate numerical integrity and high-bandwidth dataflow for production-scale CNN and Transformer workloads. Verification Methodology: Leverage SystemVerilog/UVM for Coverage-Driven Verification (CDV) to reach aggressive functional targets. Apply Formal Verification (SVA) to exhaustively prove corner cases in safety-critical arbiters, state machines, and concurrency logic where simulation falls short. Advanced Methodologies (nice-to-have): Strategize and Implement LLM-augmented workflows for Front End Development. Safety-Critical Verification (nice-to-have): Develop and execute verification plans compliant with ISO 26262 standards. Conduct Fault Injection Analysis (FIA) to verify safety mechanisms (ECC, Parity, BIST). Hardware-Software Co-Verification (nice-to-have): Collaborate with firmware teams using Emulation and FPGA prototyping to run full-stack software. Experience: Typically 10+ years of industry experience in ASIC design verification. Engineers who have seen multiple chips from "concept to tape-out." Education: BS/MS or PhD in Electrical Engineering or Computer Engineering. Hardware Knowledge: Deep understanding of Computer Architecture. Memory hierarchies (Cache, DMA, and DDR/HBM). Interconnect protocols (NoC - Network on Chip). Low-power design verification (UPF/CPF). Bonus Skills / Experience: Specialized hardware like Systolic Arrays, Vector Processors, or Neural Processing Units (NPUs). Understanding of how CNN and Transformer networks map to hardware. Compilers and toolchains