Principal Engineer, ASIC Development Engineering (Analog and Mixed Signal Design, PLL, Oscillator)

• Work as one of  the senior team members or as lead of analog IPs and deliver analog blocks on-time with state-of-the-art architecture to meet the overall product requirements
• Work closely with team in designing and delivering analog blocks
• Design analog modules from scratch
• Handling assigned tasks independently
• Pro-actively get design issues/problems resolved
• Contribute to or propose innovative design solutions and design methodologies
• Work closely with the layout engineers on providing requirements and guidelines

Education Requirements/Preference: Bachelor or Master Degree in Electrical/Electronics Engineering from reputed engineering college.

Required Work Experience:

• 8+ years of experience in Analog and mixed signal design
• Should have hands-on experience in designing analog blocks for any of the following domains:
  • Power management (voltage and current references, voltage detectors, linear and/or switching regulators)
  • Clock management (oscillators, PLL, DLL)
  • Signal processing (ADC, DAC)
• Should have solid understanding of CMOS and FinFET process technologies and associated issues in deep sub-micron technologies i.e. 7nm, 5nm and smaller.
• Should have hands-on experience in simulation of analog blocks, mixed-mode simulations, statistical simulations etc.
• Knowledge in scripting (PERL, TCL, etc.) and modelling (Matlab, VerilogA, etc.) tools will be an advantage
• Should have good insight into layouts
• Silicon debug/characterization experience is an advantage
• Should possess good documentation, communication and presentation skills
• Experience of working in a multi-site environment

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