Digital Verification Engineer

· 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.

· Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage, assertions (SVA), simulations, regression, debug, bug reporting/tracking.

· Experience in debugging RTL & Gate level simulations

· Part of multiple tapeouts with high quality verification.

· Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience

To discuss on this opportunity feel free to reach Praveen and My Number is 732-630-6121. Thanks