Principal Engineer, Product Development Engineering

Responsible for technology DPPM reduction to meet all product spec.

Responsible for NAND wafer level and Package Qualification tests setup/eFA/Action Plan;

Develop screen/stress countermeasure based on root cause analysis of failures. Providing correct test condition for the memory product and generate defined test flow for volume testing needs;

Performing deep electrical failure analysis during new product development and ramping phase. Shoot failures from both wafer level and package level. Create analysis report based on FA finding and define the action plans after communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.)

 Monitor wafer and package level and DPPM pareto for miscellaneous product lines. Work with FAB/device to improve and fine tune the fab process for DPPM reduction.

Bachelor degree or higher in electronic, microelectronics, electrical engineering, communication or related 

discipline.

Minimum 2 years semiconductor experience

Excellent problem-solving and analytical skills

The ability to clearly communicate and document findings

Programming experience, preferably Python and Perl tester language 

An understanding of MMC, SATA, USB or PCIE controller protocols and architectures - including datasheet specs, timings, etc.

A basic background in NAND flash operation, including data sheet knowledge of specifications and timings, etc.

Experience with NAND and/or Controller debug and testing

Willingness to travel abroad for short periods

PREFERRED

3D NAND production experience, and also EFA/PFA experience.

Experience in Automatic Test Equipment platforms code development (for example, Advantest, Verigy/Agilent 93000, Credence, LTX, Teradyne, etc.)

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