Job Details:

Job Description: 

The Role and Impact Join Intel's innovative team as an IP Logic Design Engineer, where you will contribute to the creation of cutting-edge semiconductor technologies. This role is pivotal in designing and optimizing Intellectual Property (IP) blocks integral to next-generation Custom System-on-Chip (SoC) designs. Your efforts will drive advancements in low-power, high-performance architectures, directly impacting Intel's leadership in the semiconductor industry. Collaborating with world-class engineers, you will tackle complex technical challenges and play a vital role in Intel's continued success. Key Responsibilities - Develop and implement Register Transfer Level (RTL) coding and simulations for IP blocks, ensuring seamless integration into SoC designs. - Collaborate on defining architecture and microarchitecture features for IP blocks, aligning them with system requirements. - Optimize logic designs to meet power, performance, area, and timing objectives while ensuring design integrity for physical implementation. - Debug RTL designs and resolve test failures to ensure correctness and high-quality delivery of features. - Perform front-end quality checks, including CDC, RDC, LINT, synthesis, and timing closure. - Support SoC customers during IP integration and verification, addressing technical issues as needed. - Review verification plans to validate design features and implement corrective measures for any discrepancies. - Drive quality assurance compliance for smooth IP-SoC handoff and integration processes.

Qualifications:

Minimum Qualifications - Bachelor's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field, with 8+ years of experience in digital design and RTL coding. A Master's degree with 6+ years of experience or a PhD with 4+ years of experience may also qualify. - Proficiency in RTL design, System Verilog, and low-power design methodologies. - Hands-on experience with front-end tools such as CDC, RDC, LINT, synthesis, and timing closure. - Advanced knowledge of protocols including PCIe, AXI, AHB, and APB. - Expertise in UPF low-power coding, clock gating, clock domain crossing, and power gating techniques. - Experience debugging RTL designs, writing verification testbenches, and using scripting languages such as TCL. Preferred Qualifications - Master's degree or PhD in Electronics Engineering, Computer Engineering, or a related field. - Proven track record of collaboration across functional teams and solving complex design challenges. - Strong communication skills and the ability to effectively articulate technical concepts. Explore the opportunity to be part of Intel's transformative innovations and contribute to shaping the future of semiconductor technology. Apply today to advance your career and help drive meaningful change.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.