Job Details:

Job Description: 

Join us as a CPU DFD (Design-For-Debug) Validation Engineer and play a pivotal role in shaping the future of next generation of Intel CPU. In this role, you will ensure the reliability and functionality of cutting-edge CPUs by verifying DFD logic designs against specifications, and will develop various debug solutions in the form of software to support in-house post-silicon validation and external customers. This is a unique opportunity to collaborate with industry-leading architects, designers, and engineers to refine and advance Intel's CPU microarchitecture.

Key Responsibilities

• Develop comprehensive DFD verification plans, test benches, and environments to achieve full coverage of DFD functionality against CPU microarchitecture specifications.

• Define and execute verification plans, run system simulation/emulation/FPGA models, analyze power and timing, and uncover bugs in the design.

• Develop software solution to support in-house post-silicon validation activities and external customers, and provide necessary post-silicon debug support as needed to internal validation/manufacturing and external customers

• Replicate, root cause, and debug issues in both pre-silicon and post-silicon environments, implementing corrective actions as needed.

• Collaborate with CPU architects, RTL developers, and physical design teams to ensure DFD usage models are viable for post-silicon debug usages

• Document detailed test plans and lead technical reviews with design and architecture teams.

• Maintain and improve existing functional verification infrastructure and methodologies.

• Contribute to the definition and development of innovative DFD architecture/microarchitecture features within the CPU design process.

Qualifications:

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

• 2+ years of experience with a Bachelor's degree / Master's degree, or PhD graduate.

• Proficiency in System Verilog and UVM for pre-silicon verification.

• Strong scripting and programming skills in languages, particularly Python, Perl and C/C++.

• Robust understanding of CPU architecture and microarchitecture fundamentals.

• Proficiency in System Verilog and UVM, and with experience debugging any DFx issue in pre-silicon environment.

• Strong problem-solving and analytical skills with a creative approach to debugging and resolving issues.

• Effective communication and collaboration skills to work cohesively in a dynamic, fast-paced environment.

• Self-motivated individual with a passion for innovation and continuous learning.

Preferred Qualifications

• Proven expertise/knowledge in TAP (Test Access Port).

• Prior knowledge in ASIC or FPGA design verification, particularly with x86 CPU designs.

• Prior knowledge in the use of emulation/FPGA for software/application prototyping.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.