Senior Physical Design Engineer

This role is for one of the Weekday's clients

Salary range: Rs 1800000 - Rs 6000000 (ie INR 18-60 LPA)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-Time

We are looking for an experienced Senior Physical Design Engineer to join a high-performance VLSI engineering team working on advanced ASIC and SoC designs across leading-edge technology nodes. In this role, you will be responsible for driving the complete physical design implementation from RTL handoff to GDSII while ensuring optimal performance, power, area, and timing closure.

The ideal candidate will have strong hands-on expertise in Place and Route (PnR), floorplanning, timing analysis, and physical signoff, along with the ability to collaborate across multiple design disciplines to deliver high-quality silicon.

Key Responsibilities

• Execute the complete RTL-to-GDSII Physical Design flow for complex ASIC and SoC designs.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Drive timing closure, signal integrity (SI) closure, power optimization, and area optimization to achieve design targets.
• Perform MCMM timing analysis and static timing analysis (STA) using industry-standard timing tools.
• Resolve DRC, LVS, and physical signoff issues while ensuring design quality and manufacturability.
• Implement Engineering Change Orders (ECOs) and support successful tape-out activities.
• Collaborate closely with RTL, DFT, STA, Verification, and other cross-functional engineering teams throughout the design lifecycle.
• Develop and maintain TCL automation scripts to improve design efficiency and productivity.
• Analyze and optimize designs for IR drop, electromigration (EM), crosstalk, and low-power implementation requirements.
• Contribute to continuous improvement of physical design methodologies, automation, and best practices.

What Makes You a Great Fit

• 4+ years of hands-on experience in Physical Design for ASIC or SoC development.
• Strong expertise in Place and Route (PnR) using ICC2 and/or Fusion Compiler.
• Solid experience with Floorplanning , power planning, CTS, routing, timing closure, and physical signoff.
• Strong understanding of Static Timing Analysis (STA) and MCMM timing analysis using PrimeTime or equivalent tools.
• Experience working on advanced semiconductor technology nodes such as 16nm, 7nm, 5nm, or 3nm.
• Good knowledge of IR Drop analysis, electromigration (EM), crosstalk, and low-power implementation methodologies.
• Strong TCL scripting skills for automation and productivity enhancement.
• Familiarity with tools such as Innovus, Tempus, Genus, RedHawk, StarRC, or Calibre is an added advantage.
• Knowledge of Python or Shell scripting, UPF, hierarchical SoC implementation, and low-power design techniques is preferred.
• Excellent analytical, debugging, and problem-solving skills with the ability to work effectively in cross-functional engineering environments.