At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a Design Engineer (7-12 years) to join our PCIe Design Team, working on next‑generation high‑speed interface IPs.

🔹 Key Responsibilities & Skills

Must Have : Hands‑on experience in PCIe design and micro‑architecture

Strong proficiency with design tools and a solid understanding of PPA (Performance, Power, Area) optimization techniques

Must Have : Good knowledge of scripting and applying AI-assisted design tools in the development flow

Strong debug skills and ability to collaborate closely with DV teams to resolve design issues

Highly Desired Skill : knowledge on Integrity and Data Encryption (IDE) : AES Encryption/Decryption algorithm along with GCM protocol.

Desired Skill : Automotive/FuSa experience

🎓 Qualifications

B.Tech / M.Tech in Electronics, Electrical, or Computer Science

If you’re passionate about high-speed interfaces and enjoy working on complex, performance‑critical designs, we’d love to connect.

Principal Design Engineer